Publications

  • 2025:
    1. Low-Latency Transaction Scheduling via Userspace Interrupts: Why Wait or Yield When You Can Preempt?. K. Huang, J. Zhou, Z. Zhao, D. Xie and T. Wang. Proc. ACM Manag. Data, 3(3):182:1–182:25, 2025. [ link ]
    2. Tabular: Efficiently Building Efficient Indexes. Z. Yan, M. Drira, T. Hu and T. Wang. Proc. VLDB Endow., 18(6):1991–2004, 2025. [ link ]
    3. Accio: Bolt-on Query Federation. X. Wang, J. Wang, T. Wang and Y. Zhang. Proc. VLDB Endow., 18(7):2126–2135, 2025. [ link ]
    4. Analytics Are Heavy. The DBMS Is Busy. When Will My Mission-Critical Transaction Start Running?. J. Zhou, K. Huang, Z. Zhao, D. Xie and T. Wang. Proc. VLDB Endow., 18(12):5299–5302, 2025. [ link ]
    5. RANGE-BLOCKS: A Synchronization Facility for Domain-Specific Architectures. A. Kumar, A. Prasanna and A. Shriraman. In Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1, ASPLOS 2025, Rotterdam, The Netherlands, 30 March 2025 - 3 April 2025. ACM, pp. 891–906, 2025. [ link ]
  • 2024:
    1. Contigra: Graph Mining with Containment Constraints. J. Che, K. Jamshidi and K. Vora. In Proceedings of the Nineteenth European Conference on Computer Systems, EuroSys 2024, Athens, Greece, April 22-25, 2024. ACM, pp. 50–65, 2024. [ link ]
    2. OsirisBFT: Say No to Task Replication for Scalable Byzantine Fault Tolerant Analytics. K. Jamshidi and K. Vora. In Proceedings of the 29th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming, PPoPP 2024, Edinburgh, United Kingdom, March 2-6, 2024. ACM, pp. 94–108, 2024. [ link ]
    3. DEX: Scalable Range Indexing on Disaggregated Memory. B. Lu, K. Huang, C. Liang, T. Wang and E. Lo. Proc. VLDB Endow., 17(10):2603–2616, 2024. [ link ]
    4. Second Workshop on Simplicity in Management of Data (SiMoD). D. Porobic and T. Wang. In Companion of the 2024 International Conference on Management of Data, SIGMOD⁄PODS 2024, Santiago, Chile, June 9-15, 2024. ACM, pp. 647–648, 2024. [ link ]
    5. METAL: Caching Multi-level Indexes in Domain-Specific Architectures. A. Kumar, A. Prasanna, J. Balkind and A. Shriraman. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2, ASPLOS 2024, La Jolla, CA, USA, 27 April 2024- 1 May 2024. ACM, pp. 715–729, 2024. [ link ]
    6. TapeFlow: Streaming Gradient Tapes in Automatic Differentiation. M. Hakimi and A. Shriraman. In IEEE⁄ACM International Symposium on Code Generation and Optimization, CGO 2024, Edinburgh, United Kingdom, March 2-6, 2024. IEEE, pp. 81–92, 2024. [ link ]
  • 2023:
    1. Accelerating Graph Mining Systems with Subgraph Morphing. K. Jamshidi, H. Xu and K. Vora. In Proceedings of the Eighteenth European Conference on Computer Systems, EuroSys 2023, Rome, Italy, May 8-12, 2023. ACM, pp. 162–181, 2023. [ link ]
    2. OptiQL: Robust Optimistic Locking for Memory-Optimized Indexes. G. Shi, Z. Yan and T. Wang. Proc. ACM Manag. Data, 1(3):216:1–216:26, 2023. [ link ]
    3. Blink-hash: An Adaptive Hybrid Index for In-Memory Time-Series Databases. H. Cha, X. Hao, T. Wang, H. Zhang, A. Akella and X. Yu. Proc. VLDB Endow., 16(6):1235–1248, 2023. [ link ]
    4. NV-SQL: Boosting OLTP Performance with Non-Volatile DIMMs. M. An, J. Park, T. Wang, B. Nam and S. Lee. Proc. VLDB Endow., 16(6):1453–1465, 2023. [ link ]
    5. The Art of Latency Hiding in Modern Database Engines. K. Huang, T. Wang, Q. Zhou and Q. Meng. Proc. VLDB Endow., 17(3):577–590, 2023. [ link ]
    6. Efficiently Making Cross-Engine Transactions Consistent. J. Zhang, K. Huang, T. Wang and K. Lv. SIGMOD Rec., 52(1):27–34, 2023. [ link ]
    7. Future Database Engine Development: You Will Only Need One Programming Language. T. Wang. SIGMOD Rec., 52(4):39–40, 2023. [ link ]
    8. Data Pipes: Declarative Control over Data Movement. L. Vogel, D. Ritter, D. Porobic, P. Tözün, T. Wang and A. Lerner. In 13th Conference on Innovative Data Systems Research, CIDR 2023, Amsterdam, The Netherlands, January 8-11, 2023. www.cidrdb.org, 2023. [ link ]
    9. Workshop on Simplicity in Management of Data (SiMoD). D. Porobic and T. Wang. In Companion of the 2023 International Conference on Management of Data, SIGMOD⁄PODS 2023, Seattle, WA, USA, June 18-23, 2023. ACM, pp. 301–302, 2023. [ link ]
    10. Proceedings of the 1st Workshop on Simplicity in Management of Data, SiMoD@SIGMOD 2023, Bellevue, WA, USA, 23 June 2023. D. Porobic and T. Wang, editors. 2023. [ link ]
  • 2022:
    1. Anti-vertex for neighborhood constraints in subgraph queries. K. Jamshidi, M. Mariappan and K. Vora. In GRADES-NDA ’22: Proceedings of the 5th ACM SIGMOD Joint International Workshop on Graph Data Management Experiences & Systems (GRADES) and Network Data Analytics (NDA), Philadelphia, Pennsylvania, USA, 12 June 2022. ACM, pp. 5:1–5:9, 2022. [ link ]
    2. Evaluating Persistent Memory Range Indexes: Part Two. Y. He, D. Lu, K. Huang and T. Wang. Proc. VLDB Endow., 15(11):2477–2490, 2022. [ link ]
    3. ConnectorX: Accelerating Data Loading From Databases to Dataframes. X. Wang, W. Wu, J. Wu, Y. Chen, N. Zrymiak, C. Qu, L. Flokas, G. Chow, J. Wang, T. Wang, E. Wu and Q. Zhou. Proc. VLDB Endow., 15(11):2994–3003, 2022. [ link ]
    4. Are Updatable Learned Indexes Ready?. C. Wongkham, B. Lu, C. Liu, Z. Zhong, E. Lo and T. Wang. Proc. VLDB Endow., 15(11):3004–3017, 2022. [ link ]
    5. The Past, Present and Future of Indexing on Persistent Memory. K. Huang, Y. He and T. Wang. Proc. VLDB Endow., 15(12):3774–3777, 2022. [ link ]
    6. Online Schema Evolution is (almost) Free for Snapshot Databases. T. Hu, T. Wang and Q. Zhou. Proc. VLDB Endow., 16(2):140–153, 2022. [ link ]
    7. SSDs Striking Back: The Storage Jungle and Its Implications to Persistent Indexes. K. Huang, D. Imai, T. Wang and D. Xie. In 12th Conference on Innovative Data Systems Research, CIDR 2022, Chaminade, CA, USA, January 9-12, 2022. www.cidrdb.org, 2022. [ link ]
    8. Skeena: Efficient and Consistent Cross-Engine Transactions. J. Zhang, K. Huang, T. Wang and K. Lv. In SIGMOD ’22: International Conference on Management of Data, Philadelphia, PA, USA, June 12 - 17, 2022. ACM, pp. 34–48, 2022. [ link ]
    9. mu-grind: A Framework for Dynamically Instrumenting HLS-Generated RTL. P. Vahdatniya, A. Sharifian, R. Hojabr and A. Shriraman. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, PACT 2022, Chicago, Illinois, October 8-12, 2022. ACM, pp. 346–358, 2022. [ link ]
    10. X-cache: a modular architecture for domain-specific caches. A. Sedaghati, M. Hakimi, R. Hojabr and A. Shriraman. In ISCA ’22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18 - 22, 2022. ACM, pp. 396–409, 2022. [ link ]
  • 2021:
    1. Grafs: declarative graph analytics. F. Houshmand, M. Lesani and K. Vora. Proc. ACM Program. Lang., 5({ICFP}):1–32, 2021. [ link ]
    2. A Deeper Dive into Pattern-Aware Subgraph Exploration with PEREGRINE. K. Jamshidi and K. Vora. ACM SIGOPS Oper. Syst. Rev., 55(1):1–10, 2021. [ link ]
    3. DZiG: sparsity-aware incremental processing of streaming graphs. M. Mariappan, J. Che and K. Vora. In EuroSys ’21: Sixteenth European Conference on Computer Systems, Online Event, United Kingdom, April 26-28, 2021. ACM, pp. 83–98, 2021. [ link ]
    4. Dorylus: Affordable, Scalable, and Accurate GNN Training with Distributed CPU Servers and Serverless Threads. J. Thorpe, Y. Qiao, J. Eyolfson, S. Teng, G. Hu, Z. Jia, J. Wei, K. Vora, R. Netravali, M. Kim and G. Xu. In 15th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2021, July 14-16, 2021. USENIX Association, pp. 495–514, 2021. [ link ]
    5. Controlling Memory Footprint of Stateful Streaming Graph Processing. P. Vaziri and K. Vora. In Proceedings of the 2021 USENIX Annual Technical Conference, USENIX ATC 2021, July 14-16, 2021. USENIX Association, pp. 269–283, 2021. [ link ]
    6. APEX: A High-Performance Learned Index on Persistent Memory. B. Lu, J. Ding, E. Lo, U. Minhas and T. Wang. Proc. VLDB Endow., 15(3):597–610, 2021. [ link ]
    7. Scaling Dynamic Hash Tables on Real Persistent Memory. B. Lu, X. Hao, T. Wang and E. Lo. SIGMOD Rec., 50(1):87–94, 2021. [ link ]
    8. X-Layer: Building Composable Pipelined Dataflows for Low-Rank Convolutions. N. Vedula, R. Hojabr, A. Khonsari and A. Shriraman. In 30th International Conference on Parallel Architectures and Compilation Techniques, PACT 2021, Atlanta, GA, USA, September 26-29, 2021. IEEE, pp. 103–115, 2021. [ link ]
    9. SPAGHETTI: Streaming Accelerators for Highly Sparse GEMM on FPGAs. R. Hojabr, A. Sedaghati, A. Sharifian, A. Khonsari and A. Shriraman. In IEEE International Symposium on High-Performance Computer Architecture, HPCA 2021, Seoul, South Korea, February 27 - March 3, 2021. IEEE, pp. 84–96, 2021. [ link ]
    10. Real-Time Hamilton-Jacobi Reachability Analysis of Autonomous System With An FPGA. M. Bui, M. Lu, R. Hojabr, M. Chen and A. Shriraman. In IEEE⁄RSJ International Conference on Intelligent Robots and Systems, IROS 2021, Prague, Czech Republic, September 27 - Oct. 1, 2021. IEEE, pp. 1666–1673, 2021. [ link ]
  • 2020:
    1. Peregrine: a pattern-aware graph mining system. K. Jamshidi, R. Mahadasa and K. Vora. In EuroSys ’20: Fifteenth EuroSys Conference 2020, Heraklion, Greece, April 27-30, 2020. ACM, pp. 13:1–13:16, 2020. [ link ]
    2. Dash: Scalable Hashing on Persistent Memory. B. Lu, X. Hao, T. Wang and E. Lo. Proc. VLDB Endow., 13(8):1147–1161, 2020. [ link ]
    3. PiBench Online: Interactive Benchmarking of Persistent Memory Indexes. X. Hao, L. Lersch, T. Wang and I. Oukid. Proc. VLDB Endow., 13(12):2817–2820, 2020. [ link ]
    4. CoroBase: Coroutine-Oriented Main-Memory Database Engine. Y. He, J. Lu and T. Wang. Proc. VLDB Endow., 14(3):431–444, 2020. [ link ]
    5. Parallelizing Filter-Verification Based Exact Set Similarity Joins on Multicores. F. Fier, T. Wang, E. Zhu and J. Freytag. In Similarity Search and Applications - 13th International Conference, SISAP 2020, Copenhagen, Denmark, September 30 - October 2, 2020, Proceedings. Springer, Lecture Notes in Computer Science 12440, pp. 62–75, 2020. [ link ]
    6. Safety-Guaranteed Real-Time Trajectory Planning for Underwater Vehicles in Plane-Progressive Waves. S. Siriya, M. Bui, A. Shriraman, M. Chen and Y. Pu. In 59th IEEE Conference on Decision and Control, CDC 2020, Jeju Island, South Korea, December 14-18, 2020. IEEE, pp. 5249–5254, 2020. [ link ]
  • 2019:
    1. Annotation guided collection of context-sensitive parallel execution profiles. Z. Benavides, K. Vora, R. Gupta and X. Zhang. Formal Methods Syst. Des., 54(3):388–415, 2019. [ link ]
    2. DProf: distributed profiler with strong guarantees. Z. Benavides, K. Vora and R. Gupta. Proc. ACM Program. Lang., 3({OOPSLA}):156:1–156:24, 2019. [ link ]
    3. PnP: Pruning and Prediction for Point-To-Point Iterative Graph Analytics. C. Xu, K. Vora and R. Gupta. In Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2019, Providence, RI, USA, April 13-17, 2019. ACM, pp. 587–600, 2019. [ link ]
    4. GraphBolt: Dependency-Driven Synchronous Processing of Streaming Graphs. M. Mariappan and K. Vora. In Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019. ACM, pp. 25:1–25:16, 2019. [ link ]
    5. LUMOS: Dependency-Driven Disk-based Graph Processing. K. Vora. In Proceedings of the 2019 USENIX Annual Technical Conference, USENIX ATC 2019, Renton, WA, USA, July 10-12, 2019. USENIX Association, pp. 429–442, 2019. [ link ]
    6. Evaluating Persistent Memory Range Indexes. L. Lersch, X. Hao, I. Oukid, T. Wang and T. Willhalm. Proc. VLDB Endow., 13(4):574–587, 2019. [ link ]
    7. DPI: The Data Processing Interface for Modern Networks. G. Alonso, C. Binnig, I. Pandis, K. Salem, J. Skrzypczak, R. Stutsman, L. Thostrup, T. Wang, Z. Wang and T. Ziegler. In 9th Biennial Conference on Innovative Data Systems Research, CIDR 2019, Asilomar, CA, USA, January 13-16, 2019, Online Proceedings. www.cidrdb.org, 2019. [ link ]
    8. Deepframe: A Profile-Driven Compiler for Spatial Hardware Accelerators. A. Guha, N. Vedula and A. Shriraman. In 28th International Conference on Parallel Architectures and Compilation Techniques, PACT 2019, Seattle, WA, USA, September 23-26, 2019. IEEE, pp. 68–81, 2019. [ link ]
    9. \(μ\)IR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators. A. Sharifian, R. Hojabr, N. Rahimi, S. Liu, A. Guha, T. Nowatzki and A. Shriraman. In Proceedings of the 52nd Annual IEEE⁄ACM International Symposium on Microarchitecture, MICRO 2019, Columbus, OH, USA, October 12-16, 2019. ACM, pp. 940–953, 2019. [ link ]
  • 2018:
    1. Software Speculation on Caching DSMs. S. Koduru, K. Vora and R. Gupta. Int. J. Parallel Program., 46(2):313–332, 2018. [ link ]
    2. OMR: out-of-core MapReduce for large data sets. G. Kaur, K. Vora, S. Koduru and R. Gupta. In Proceedings of the 2018 ACM SIGPLAN International Symposium on Memory Management, ISMM 2018, Philadelphia, PA, USA, June 18, 2018. ACM, pp. 71–83, 2018. [ link ]
    3. Fast and Robust Transaction Processing on Emerging Hardware. T. Wang. PhD thesis, University of Toronto, Canada, 2018. [ link ]
    4. Erratum to: Efficiently making (almost) any concurrency control mechanism serializable. T. Wang, R. Johnson, A.D. Fekete and I. Pandis. VLDB J., 27(6):899–900, 2018. [ link ]
    5. Easy Lock-Free Indexing in Non-Volatile Memory. T. Wang, J.J. Levandoski and P. Larson. In 34th IEEE International Conference on Data Engineering, ICDE 2018, Paris, France, April 16-19, 2018. IEEE Computer Society, pp. 461–472, 2018. [ link ]
    6. NACHOS: Software-Driven Hardware-Assisted Memory Disambiguation for Accelerators. N. Vedula, A. Shriraman, S. Kumar and W.N. Sumner. In IEEE International Symposium on High Performance Computer Architecture, HPCA 2018, Vienna, Austria, February 24-28, 2018. IEEE Computer Society, pp. 710–723, 2018. [ link ]
    7. TAPAS: Generating Parallel Accelerators from Parallel Programs. S. Margerm, A. Sharifian, A. Guha, A. Shriraman and G. Pokam. In 51st Annual IEEE⁄ACM International Symposium on Microarchitecture, MICRO 2018, Fukuoka, Japan, October 20-24, 2018. IEEE Computer Society, pp. 245–257, 2018. [ link ]
    8. Scalable distributed visual computing for line-rate video streams. C. Song, J. Chen, R. Shea, A. Sun, A. Shriraman and J. Liu. In Proceedings of the 9th ACM Multimedia Systems Conference, MMSys 2018, Amsterdam, The Netherlands, June 12-15, 2018. ACM, pp. 186–194, 2018. [ link ]
  • 2017:
    1. Exploiting Asynchrony for Performance and Fault Tolerance in Distributed Graph Processing. K. Vora. PhD thesis, University of California, Riverside, USA, 2017. [ link ]
    2. CoRAL: Confined Recovery in Distributed Asynchronous Graph Processing. K. Vora, C. Tian, R. Gupta and Z. Hu. In Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2017, Xi’an, China, April 8-12, 2017. ACM, pp. 223–236, 2017. [ link ]
    3. KickStarter: Fast and Accurate Computations on Streaming Graphs via Trimmed Approximations. K. Vora, R. Gupta and G. Xu. In Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2017, Xi’an, China, April 8-12, 2017. ACM, pp. 237–251, 2017. [ link ]
    4. Enabling Work-Efficiency for High Performance Vertex-Centric Graph Analytics on GPUs. F. Khorasani, K. Vora, R. Gupta and L.N. Bhuyan. In Proceedings of the Seventh Workshop on Irregular Applications: Architectures and Algorithms, IA3@SC 2017, Denver, CO, USA, November 12 - 17, 2017. ACM, pp. 11:1–11:4, 2017. [ link ]
    5. Fine grained, direct access file system support for storage class memory. Y. Wang, T. Wang, D. Liu, Z. Shao and J. Xue. J. Syst. Archit., 72:80–92, 2017. [ link ]
    6. Query Fresh: Log Shipping on Steroids. T. Wang, R. Johnson and I. Pandis. Proc. VLDB Endow., 11(4):406–419, 2017. [ link ]
    7. Durable Address Translation in PCM-Based Flash Storage Systems. D. Liu, K. Zhong, T. Wang, Y. Wang, Z. Shao, E. Sha and J. Xue. IEEE Trans. Parallel Distributed Syst., 28(2):475–490, 2017. [ link ]
    8. Efficiently making (almost) any concurrency control mechanism serializable. T. Wang, R. Johnson, A.D. Fekete and I. Pandis. VLDB J., 26(4):537–562, 2017. [ link ]
    9. Needle: Leveraging Program Analysis to Analyze and Extract Accelerators from Whole Programs. S. Kumar, N. Sumner, V. Srinivasan, S. Margerm and A. Shriraman. In 2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017. IEEE Computer Society, pp. 565–576, 2017. [ link ]
  • 2016:
    1. Synergistic Analysis of Evolving Graphs. K. Vora, R. Gupta and G. Xu. ACM Trans. Archit. Code Optim., 13(4):32:1–32:27, 2016. [ link ]
    2. Efficient Processing of Large Graphs via Input Reduction. A. Kusum, K. Vora, R. Gupta and I. Neamtiu. In Proceedings of the 25th ACM International Symposium on High-Performance Parallel and Distributed Computing, HPDC 2016, Kyoto, Japan, May 31 - June 04, 2016. ACM, pp. 245–257, 2016. [ link ]
    3. Load the Edges You Need: A Generic I⁄O Optimization for Disk-based Graph Processing. K. Vora, G. Xu and R. Gupta. In Proceedings of the 2016 USENIX Annual Technical Conference, USENIX ATC 2016, Denver, CO, USA, June 22-24, 2016. USENIX Association, pp. 507–522, 2016. [ link ]
    4. Mostly-Optimistic Concurrency Control for Highly Contended Dynamic Workloads on a Thousand Cores. T. Wang and H. Kimura. Proc. VLDB Endow., 10(2):49–60, 2016. [ link ]
    5. Be my guest: MCS lock now welcomes guests. T. Wang, M. Chabbi and H. Kimura. In Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2016, Barcelona, Spain, March 12-16, 2016. ACM, pp. 21:1–21:12, 2016. [ link ]
    6. ERMIA: Fast Memory-Optimized Database System for Heterogeneous Workloads. K. Kim, T. Wang, R. Johnson and I. Pandis. In Proceedings of the 2016 International Conference on Management of Data, SIGMOD Conference 2016, San Francisco, CA, USA, June 26 - July 01, 2016. ACM, pp. 1675–1687, 2016. [ link ]
    7. How to Speed Up CUDA-WSat-PcL by 5x. H. Liu, A. Shriraman and E. Ternovska. In Fourth International Symposium on Computing and Networking, CANDAR 2016, Hiroshima, Japan, November 22-25, 2016. IEEE Computer Society, pp. 462–468, 2016. [ link ]
    8. Peruse and Profit: Estimating the Accelerability of Loops. S. Kumar, V. Srinivasan, A. Sharifian, N. Sumner and A. Shriraman. In Proceedings of the 2016 International Conference on Supercomputing, ICS 2016, Istanbul, Turkey, June 1-3, 2016. ACM, pp. 21:1–21:13, 2016. [ link ]
    9. SPEC-AX and PARSEC-AX: extracting accelerator benchmarks from microprocessor benchmarks. S. Kumar, W.N. Sumner and A. Shriraman. In 2016 IEEE International Symposium on Workload Characterization, IISWC 2016, Providence, RI, USA, September 25-27, 2016. IEEE Computer Society, pp. 117–127, 2016. [ link ]
    10. Chainsaw: Von-neumann accelerators to leverage fused instruction chains. A. Sharifian, S. Kumar, A. Guha and A. Shriraman. In 49th Annual IEEE⁄ACM International Symposium on Microarchitecture, MICRO 2016, Taipei, Taiwan, October 15-19, 2016. IEEE Computer Society, pp. 49:1–49:14, 2016. [ link ]
  • 2015:
    1. Optimizing Caching DSM for Distributed Software Speculation. S. Koduru, K. Vora and R. Gupta. In 2015 IEEE International Conference on Cluster Computing, CLUSTER 2015, Chicago, IL, USA, September 8-11, 2015. IEEE Computer Society, pp. 452–455, 2015. [ link ]
    2. RAIVE: runtime assessment of floating-point instability by vectorization. W. Lee, T. Bao, Y. Zheng, X. Zhang, K. Vora and R. Gupta. In Proceedings of the 2015 ACM SIGPLAN International Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA 2015, part of SPLASH 2015, Pittsburgh, PA, USA, October 25-30, 2015. ACM, pp. 623–638, 2015. [ link ]
    3. Towards Write-Activity-Aware Page Table Management for Non-volatile Main Memories. T. Wang, D. Liu, Y. Wang and Z. Shao. ACM Trans. Embed. Comput. Syst., 14(2):34:1–34:23, 2015. [ link ]
    4. The Serial Safety Net: Efficient Concurrency Control on Modern Hardware. T. Wang, R. Johnson, A.D. Fekete and I. Pandis. In Proceedings of the 11th International Workshop on Data Management on New Hardware, DaMoN 2015, Melbourne, VIC, Australia, May 31 - June 04, 2015. ACM, pp. 8:1–8:8, 2015. [ link ]
    5. File system-independent block device support for storage class memory. Y. Wang, T. Wang, Z. Shao, D. Liu and J. Xue. In 2015 IEEE Conference on Computer Communications Workshops, INFOCOM Workshops, Hong Kong, China, April 26 - May 1, 2015. IEEE, pp. 468–473, 2015. [ link ]
    6. DASX: Hardware Accelerator for Software Data Structures. S. Kumar, N. Vedula, A. Shriraman and V. Srinivasan. In Proceedings of the 29th ACM on International Conference on Supercomputing, ICS’15, Newport Beach⁄Irvine, CA, USA, June 08 - 11, 2015. ACM, pp. 361–372, 2015. [ link ]
    7. Fusion: design tradeoffs in coherent cache hierarchies for accelerators. S. Kumar, A. Shriraman and N. Vedula. In Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015. ACM, pp. 733–745, 2015. [ link ]
  • 2014:
    1. CuSha: vertex-centric graph processing on GPUs. F. Khorasani, K. Vora, R. Gupta and L.N. Bhuyan. In The 23rd International Symposium on High-Performance Parallel and Distributed Computing, HPDC’14, Vancouver, BC, Canada - June 23 - 27, 2014. ACM, pp. 239–252, 2014. [ link ]
    2. ABC2: Adaptively Balancing Computation and Communication in a DSM Cluster of Multicores for Irregular Applications. S. Koduru, K. Vora and R. Gupta. In 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, Phoenix, AZ, USA, May 19-23, 2014. IEEE Computer Society, pp. 391–400, 2014. [ link ]
    3. ASPIRE: exploiting asynchronous parallelism in iterative algorithms using a relaxed consistency based DSM. K. Vora, S. Koduru and R. Gupta. In Proceedings of the 2014 ACM International Conference on Object Oriented Programming Systems Languages & Applications, OOPSLA 2014, part of SPLASH 2014, Portland, OR, USA, October 20-24, 2014. ACM, pp. 861–878, 2014. [ link ]
    4. Scalable Logging through Emerging Non-Volatile Memory. T. Wang and R. Johnson. Proc. VLDB Endow., 7(10):865–876, 2014. [ link ]
    5. Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems. D. Liu, T. Wang, Y. Wang, Z. Shao, Q. Zhuge and E. Sha. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33(10):1450–1462, 2014. [ link ]
    6. Deterministic Crash Recovery for NAND Flash Based Storage Systems. C. Zhang, Y. Wang, T. Wang, R. Chen, D. Liu and Z. Shao. In The 51st Annual Design Automation Conference 2014, DAC ’14, San Francisco, CA, USA, June 1-5, 2014. ACM, pp. 148:1–148:6, 2014. [ link ]
    7. Building high-performance smartphones via non-volatile memory: The swap approach. K. Zhong, T. Wang, X. Zhu, L. Long, D. Liu, W. Liu, Z. Shao and E. Sha. In 2014 International Conference on Embedded Software, EMSOFT 2014, New Delhi, India, October 12-17, 2014. ACM, pp. 30:1–30:10, 2014. [ link ]
    8. DR. Swap: energy-efficient paging for smartphones. K. Zhong, X. Zhu, T. Wang, D. Zhang, X. Luo, D. Liu, W. Liu and E. Sha. In International Symposium on Low Power Electronics and Design, ISLPED’14, La Jolla, CA, USA - August 11 - 13, 2014. ACM, pp. 81–86, 2014. [ link ]
    9. Robust concurrency control in main-memory DBMS: What main memory giveth, the application taketh away. R. Johnson, K. Kim, T. Wang and I. Pandis. In Proceedings of the 2nd International Workshop on In Memory Data Management and Analytics, IMDM 2014, Hangzhou, China, September 1, 2014. pp. 57–59, 2014. [ link ]
    10. Cache Coherence for GPU Architectures. I. Singh, A. Shriraman, W.W.L. Fung, M. O’Connor and T.M. Aamodt. IEEE Micro, 34(3):69–79, 2014. [ link ]
    11. Bitwise data parallelism in regular expression matching. R.D. Cameron, T.C. Shermer, A. Shriraman, K.S. Herdy, D. Lin, B.R. Hull and M. Lin. In International Conference on Parallel Architectures and Compilation, PACT ’14, Edmonton, AB, Canada, August 24-27, 2014. ACM, pp. 139–150, 2014. [ link ]
    12. SQRL: hardware accelerator for collecting software data structures. S. Kumar, A. Shriraman, V. Srinivasan, D. Lin and J. Phillips. In International Conference on Parallel Architectures and Compilation, PACT ’14, Edmonton, AB, Canada, August 24-27, 2014. ACM, pp. 475–476, 2014. [ link ]
  • 2013:
    1. Curling-PCM: Application-specific wear leveling for phase change memory based embedded systems. D. Liu, T. Wang, Y. Wang, Z. Shao, Q. Zhuge and E. Sha. In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013. IEEE, pp. 279–284, 2013. [ link ]
    2. FTL\(^\mbox2\): a hybrid \emphflash \emphtranslation \emphlayer with logging for write reduction in flash memory. T. Wang, D. Liu, Y. Wang and Z. Shao. In SIGPLAN⁄SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2013, LCTES ’13, Seattle, WA, USA, June 20-21, 2013. ACM, pp. 91–100, 2013. [ link ]
    3. An Application-Tailored Approach to Hardware Cache Coherence. A. Shriraman, H. Zhao and S. Dwarkadas. Computer, 46(10):40–47, 2013. [ link ]
    4. Power containers: an OS facility for fine-grained power and energy management on multicore servers. K. Shen, A. Shriraman, S. Dwarkadas, X. Zhang and Z. Chen. In Architectural Support for Programming Languages and Operating Systems, ASPLOS 2013, Houston, TX, USA, March 16-20, 2013. ACM, pp. 65–76, 2013. [ link ]
    5. Verifying safety and liveness for the FlexTM hybrid transactional memory. P. Abdulla, S. Dwarkadas, A. Rezine, A. Shriraman and Y. Zhu. In Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013. EDA Consortium San Jose, CA, USA ⁄ ACM DL, pp. 785–790, 2013. [ link ]
    6. Cache coherence for GPU architectures. I. Singh, A. Shriraman, W.W.L. Fung, M. O’Connor and T.M. Aamodt. In 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 23-27, 2013. IEEE Computer Society, pp. 578–590, 2013. [ link ]
    7. Protozoa: adaptive granularity cache coherence. H. Zhao, A. Shriraman, S. Kumar and S. Dwarkadas. In The 40th Annual International Symposium on Computer Architecture, ISCA’13, Tel-Aviv, Israel, June 23-27, 2013. ACM, pp. 547–558, 2013. [ link ]
  • 2012:
    1. Write-activity-aware page table management for PCM-based embedded systems. T. Wang, D. Liu, Z. Shao and C. Yang. In Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012. IEEE, pp. 317–322, 2012. [ link ]
    2. A block-level flash memory management scheme for reducing write activities in PCM-based embedded systems. D. Liu, T. Wang, Y. Wang, Z. Qin and Z. Shao. In 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012. IEEE, pp. 1447–1450, 2012. [ link ]
    3. Parabix: Boosting the efficiency of text processing on commodity processors. D. Lin, N. Medforth, K.S. Herdy, A. Shriraman and R.D. Cameron. In 18th IEEE International Symposium on High Performance Computer Architecture, HPCA 2012, New Orleans, LA, USA, 25-29 February, 2012. IEEE Computer Society, pp. 373–384, 2012. [ link ]
    4. Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy. S. Kumar, H. Zhao, A. Shriraman, E. Matthews, S. Dwarkadas and L. Shannon. In 45th Annual IEEE⁄ACM International Symposium on Microarchitecture, MICRO 2012, Vancouver, BC, Canada, December 1-5, 2012. IEEE Computer Society, pp. 376–388, 2012. [ link ]
    5. Power and energy containers for multicore servers. K. Shen, A. Shriraman, S. Dwarkadas and X. Zhang. In ACM SIGMETRICS⁄PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS ’12, London, United Kingdom, June 11-15, 2012. ACM, pp. 403–404, 2012. [ link ]
  • 2011:
    1. PCM-FTL: A Write-Activity-Aware NAND Flash Memory Management Scheme for PCM-Based Embedded Systems. D. Liu, T. Wang, Y. Wang, Z. Qin and Z. Shao. In Proceedings of the 32nd IEEE Real-Time Systems Symposium, RTSS 2011, Vienna, Austria, November 29 - December 2, 2011. IEEE Computer Society, pp. 357–366, 2011. [ link ]
    2. Analyzing Conflicts in Hardware-Supported Memory Transactions. A. Shriraman and S. Dwarkadas. Int. J. Parallel Program., 39(1):33–61, 2011. [ link ]
    3. SPATL: Honey, I Shrunk the Coherence Directory. H. Zhao, A. Shriraman, S. Dwarkadas and V. Srinivasan. In 2011 International Conference on Parallel Architectures and Compilation Techniques, PACT 2011, Galveston, TX, USA, October 10-14, 2011. IEEE Computer Society, pp. 33–44, 2011. [ link ]
  • 2010:
    1. Implementation tradeoffs in the design of flexible transactional memory support. A. Shriraman, S. Dwarkadas and M.L. Scott. J. Parallel Distributed Comput., 70(10):1068–1084, 2010. [ link ]
    2. SPACE: sharing pattern-based directory coherence for multicore scalability. H. Zhao, A. Shriraman and S. Dwarkadas. In 19th International Conference on Parallel Architectures and Compilation Techniques, PACT 2010, Vienna, Austria, September 11-15, 2010. ACM, pp. 135–146, 2010. [ link ]
    3. Sentry: light-weight auxiliary memory access control. A. Shriraman and S. Dwarkadas. In 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France. ACM, pp. 407–418, 2010. [ link ]
  • 2009:
    1. Tapping into Parallelism with Transactional Memory. A. Shriraman, S. Dwarkadas and M.L. Scott. login Usenix Mag., 34(2), 2009. [ link ]
    2. Refereeing conflicts in hardware transactional memory. A. Shriraman and S. Dwarkadas. In Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009. ACM, pp. 136–146, 2009. [ link ]
  • 2008:
    1. Flexible Decoupled Transactional Memory Support. A. Shriraman, S. Dwarkadas and M.L. Scott. In 35th International Symposium on Computer Architecture (ISCA 2008), June 21-25, 2008, Beijing, China. IEEE Computer Society, pp. 139–150, 2008. [ link ]
  • 2007:
    1. An integrated hardware-software approach to flexible transactional memory. A. Shriraman, M.F. Spear, H. Hossain, V.J. Marathe, S. Dwarkadas and M.L. Scott. In 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA. ACM, pp. 104–115, 2007. [ link ]
    2. Alert-on-update: a communication aid for shared memory multiprocessors. M.F. Spear, A. Shriraman, H. Hossain, S. Dwarkadas and M.L. Scott. In Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2007, San Jose, California, USA, March 14-17, 2007. ACM, pp. 132–133, 2007. [ link ]
    3. Nonblocking transactions without indirection using alert-on-update. M.F. Spear, A. Shriraman, L. Dalessandro, S. Dwarkadas and M.L. Scott. In SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, San Diego, California, USA, June 9-11, 2007. ACM, pp. 210–220, 2007. [ link ]
  • 2006:
    1. PASCOM: Power Model for Supercomputers. A. Shriraman, N. Venkateswaran and N. Soundararajan. In Architecture of Computing Systems - ARCS 2006, 19th International Conference, Frankfurt⁄Main, Germany, March 13-16, 2006, Proceedings. Springer, Lecture Notes in Computer Science 3894, pp. 326–340, 2006. [ link ]
  • 2005:
    1. Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance. N. Venkateswaran, A. Shriraman and N. Soundararajan. In 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM ⁄ Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA. IEEE Computer Society, 2005. [ link ]
  • 2004:
    1. Memory in processor: a novel design paradigm for supercomputing architectures. N. Venkateswaran, A. Krishnan, N.S. Kumar, A. Shriraman and S. Sridharan. SIGARCH Comput. Archit. News, 32(3):19–26, 2004. [ link ]

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